FPGA Implementation of a Simple 3D Graphics Pipeline

doi:10.15598/aeee.v13i1.1125

Editorial board

Darius Andriukaitis
Kaunas University of Technology, Lithuania

Alexander Argyros
The University of Sydney, Australia

Radu Arsinte
Technical University of Cluj Napoca, Romania

Ivan Baronak
Slovak University of Technology, Slovakia

Khosrow Behbehani
The University of Texas at Arlington, United States

Mohamed El Hachemi Benbouzid
University of Brest, France

Dalibor Biolek
University of Defence, Czech Republic

Klara Capova
University of Zilina, Slovakia

Erik Chromy
UPC Broadband Slovakia, Slovakia

Milan Dado
University of Zilina, Slovakia

Petr Drexler
Brno University of Technology, Czech Republic

Eva Gescheidtova
Brno University of Technology, Czech Republic

Ray-Guang Cheng
National Taiwan University of Science and Technology, Taiwan, Province of China

Gokhan Hakki Ilk
Ankara University, Turkey

Janusz Jezewski
Institute of Medical Technology and Equipment, Poland

Rene Kalus
VSB - Technical University of Ostrava, Czech Republic

Ivan Kasik
Academy of Sciences of the Czech Republic, Czech Republic

Jan Kohout
University of Defence, Czech Republic

Ondrej Krejcar
University of Hradec Kralove, Czech Republic

Miroslaw Luft
Technical University of Radom, Poland

Stanislav Marchevsky
Technical University of Kosice, Slovakia

Byung-Seo Kim
Hongik University, Korea

Valeriy Arkhin
Buryat State University, Russia

Rupak Kharel
University of Huddersfield, United Kingdom

Fayaz Hussain
Ton Duc Thang University, Vietnam

Peppino Fazio
Ca’ Foscari University of Venice, Italy

Fazel Mohammadi
University of New Haven, United States of America

Thang Trung Nguyen
Ton Duc Thang University, Vietnam

Le Anh Vu
Ton Duc Thang University, Vietnam

Miroslav Voznak
VSB - Technical University of Ostrava, Czech Republic

Zbigniew Leonowicz
Wroclaw University of Science and Technology, Poland

Wasiu Oyewole Popoola
The University of Edinburgh, United Kingdom

Yuriy S. Shmaliy
Guanajuato University, Mexico

Lorand Szabo
Technical University of Cluj Napoca, Romania

Tran Trung Duy
Posts and Telecommunications Institute of Technology, Ho Chi Minh City, Vietnam

Xingwang Li
Henan Polytechnic University, China

Huynh Van Van
Ton Duc Thang University, Vietnam

Lubos Rejfek
University of Pardubice, Czech Republic

Neeta Pandey
Delhi Technological University, India

Huynh The Thien
Ho Chi Minh City University of Technology and Education, Vietnam

Mauro Tropea
DIMES Department of University of Calabria, Italy

Gaojian Huang
Henan Polytechnic University, China

Nguyen Quang Sang
Ho Chi Minh City University of Transport, Vietnam

Anh-Tu Le
Ho Chi Minh City University of Transport, Vietnam

Phu Tran Tin
Ton Duc Thang University, Vietnam

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FPGA Implementation of a Simple 3D Graphics Pipeline

Vladimir Kasik, Ales Kurecka

DOI: 10.15598/aeee.v13i1.1125

Abstract

Conventional methods for computing 3D projects are nowadays usually implemented on standard or graphics processors. The performance of these devices is limited especially by the used architecture, which to some extent works in a sequential manner. In this article we describe a project which utilizes parallel computation for simple projection of a wireframe 3D model. The algorithm is optimized for a FPGA-based implementation. The design of the numerical logic is described in VHDL with the use of several basic IP cores used especially for computing trigonometric functions. The implemented algorithms allow smooth rotation of the model in two axes (azimuth and elevation) and a change of the viewing angle. Tests carried out on a FPGA Xilinx Spartan-6 development board have resulted in real-time rendering at over 5000fps. In the conclusion of the article, we discuss additional possibilities for increasing the computational output in graphics applications via the use of HPC (High Performance Computing).